1. Field of the Invention
The present invention relates to MISFETs and, more particularly, to MISFETs capable of reducing leakage current.
2. Description of the Related Art
Since the SiGe heterojunction can be formed on a Si substrate and, in addition, has high carrier mobility, the SiGe heterojunction is expected to find applications in semiconductor devices of high-speed operation. A SiGe heteroMISFET (hereinafter will be referred to as “SiGe-HMISFET”) has been proposed as one such semiconductor device.
FIG. 19 illustrates the construction of this conventional SiGe-HMISFET; specifically, FIG. 19A is a plan view of a selectively-grown mesa structure and FIG. 19B is a sectional view taken on line XIXB—XIXB of FIG. 19A.
As shown in FIGS. 19A and 19B, the SiGe-HMISFET has n-well 10 and LOCOS (field oxide: device isolation region) 2 at surface portions of Si substrate 1. The n-well 10 is formed in active region 3, while the LOCOS 2 formed to surround the active region 3.
On the n-well 10 are formed Si buffer layer 4, SiGe channel layer 5 and Si cap layer 6 in this sequence by selective growth. The Si buffer layer 4, SiGe channel layer 5 and Si cap layer 6 form a mesa configuration as shown in FIG. 19B. Hereinafter, these layers will be generally referred to as selectively-grown mesa 21. Gate insulator 7 comprising SiO2 is formed on the selectively-grown mesa 21, specifically, on the Si cap layer 6. On the gate insulator 7 is formed gate 8 comprising polysilicon. The gate 8 is formed to extend linearly in a central portion of the selectively-grown mesa 21 in plan view, as shown in FIG. 19A. Hereinafter, this gate structure will be referred to as “I-shaped structure”. Source region 22 and drain region 23, which are doped with a p-type impurity, are formed in regions which extend over the selectively-grown mesa 21 and the surface portion of n-well 10 of the Si substrate 1 and which are situated on opposite sides of the gate 8 in plan view. A region which is situated below the gate 8 and between the source region 22 and the drain region 23 forms a channel region 24. Thus, this SiGe-HMISFET is a p-MISFET.
When the gate 8 of the SiGe-HMISFET thus constructed is applied with a voltage equal to or higher than the threshold voltage, p-channel is formed in SiGe channel layer 5c situated in the channel region 24, so that the SiGe-HMISFET functions as a transistor. Since the SiGe channel layer 5 of this transistor has high carrier mobility, the transistor operates at high speed.
There is a report that the incorporation of a SiGe channel layer into a MISFET leads to improved driving current (see Yee-chia Yeo and seven others, 0-7803-6441-4/00/$10.00C 2000IEEE for example.)
FIG. 20 is a frequency graph comparing the SiGe-HMISFET to an ordinary Si-MISFET as to frequency distribution of leakage currents.
As apparent from FIG. 20, the SiGe-HMISFET (which is of the p-channel type in FIG. 20 but may be of the n-channel type) is higher in leakage current (at a gate voltage of 0.25V) than the Si-MISFET (which is of the p-channel type in FIG. 20 but may be of the n-channel type.) Stated otherwise, the SiGe-HMISFET has a problem that leakage current occurs at low gate voltage. Though not shown, another problem with the SiGe-HMISFET is that its Ion-Ioff characteristics (subthreshold slope and threshold voltage) vary.
The ordinary Si-MISFET also involves such a leakage current problem though the leakage current value of the ordinary Si-MISFET is lower than that of the SiGe-HMISFET. It is therefore desirable to reduce the leakage current. There is a report about elucidation of the cause of occurrence of leakage current in a SOI (Silicon on Insulator)-MISFET, which is one of common MISFETs (see Toshiaki Iwamatsu and five others, IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 10, OCTOBER 1997 for example.)